1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a high-voltage semiconductor device.
2. Description of the Related Art
In general, semiconductor devices use a low power (e.g., of 3.3V or less) as supply power to reduce power consumption and to ensure reliability. However, such low power devices are generally connected to peripheral devices, which may receive a different power supply.
However, the peripheral devices often use a high voltage (e.g., of 5V or more) as supply power. Thus, many integrated circuits (IC's) include high-voltage transistors to allow a high input voltage to be supplied to the peripheral devices and/or circuits including the same from the outside.
Such a high-voltage transistor has the same structure as a normal (e.g., a low-voltage) transistor, and can be formed substantially simultaneously with the low-voltage transistor through a series of processes.
Recently, 15V bi-directional high-voltage devices have been integrated in a chip together with low-voltage devices. Such high-voltage devices can be used for output terminals of display data driver ICs in liquid crystal displays (LCDs) or organic luminescence electro displays (OLEDs).
Particularly, an exemplary number of output terminals of a display driver IC can be in a range of from 240 to 640. In addition, the uniformity of the output terminals directly exerts influences upon the uniformity of displayed images. For this reason, a uniform electrical characteristic of the output terminals is important.
Hereinafter, a method of manufacturing a high-voltage semiconductor device including a high-voltage transistor according to a related art will be described.
FIG. 1 is a sectional view of a high-voltage semiconductor device according to a related art.
As shown in FIG. 1, the high-voltage semiconductor device according to the related art includes a semiconductor substrate 1, a high-voltage p-well 2 formed on or in the semiconductor substrate 1, isolation layers 3 for defining an active region, a gate electrode 4 formed on a predetermined portion of the active region, source/drain regions 6 provided at opposite sides of the gate electrode 4, and drift regions 5 completely surrounding the source/drain regions 6 for the purpose of stability of a breakdown voltage.
At this time, since the isolation layer 3 may be obtained by forming a trench in the semiconductor substrate 1 and filling the trench with an insulating film, the thickness of the isolation layer 3 can be high relative to the depth of the source/drain regions 6 and/or the gate electrode 4.
According to the method of manufacturing a high-voltage semiconductor device, first, a predetermined portion of the semiconductor substrate 1 is masked and then impurities are implanted and diffused into the semiconductor substrate 1 through ion implantation and drive-in processes, thereby forming a high-voltage N-well (not shown) and a high voltage P-well 2 within the semiconductor substrate 1. At this time, since the drive-in process is performed at 1150° C. for 600 minutes, the depths of the high-voltage N-well and P-well become deep.
Thereafter, a mask for exposing a device isolating region is formed on the semiconductor substrate 1, and then trenches are formed by etching regions of the semiconductor substrate 1 exposed between the masks. After that, an insulating film deposited to fill the trenches. Subsequently, trench-type isolation layers 3 are formed by performing the chemical mechanical polishing (CMP) process with respect to the insulating film. Alternatively, isolation layers 3 may be formed by performing a conventional local oxidation of silicon (LOCOS) process.
Next, an N-drift region 5 and a P-drift region (not shown) are respectively formed on surfaces of the high-voltage P-well 2 and the high-voltage N-well through ion implantation of impurities. At this time, the N-drift region 5 and the P-drift region, which are low voltage N-well and P-well regions, respectively, use conventional masks applied to the conventional CMOS process.
At this time, a drift region is formed by implanting ions at an energy of 900 KeV in a 0.35 μm semiconductor process which forms gate electrodes having a CD (Critical Dimension) of about 0.35 μm. However, the drift region may be formed by implanting ions at an energy of 500 KeV in a 0.25 μm semiconductor process which forms gate electrodes having a CD of about 0.25 μm.
That is, if impurity ions are implanted at an energy of 500 KeV or more in the process of forming a 0.25 μm semiconductor device (that may be considered a highly integrated device), a large and deep impurity region is formed below a gate electrode with a short CD. Thus, a drift region in the 0.25 μm semiconductor process has a depth shallower than that in the 0.35 μm semiconductor process.
Next, gate oxide and polysilicon layers are deposited on the semiconductor substrate 1 and then simultaneously patterned, thereby forming a gate electrode 4.
In addition, source/drain regions 6 are formed at opposite sides of the gate electrode 4 of a high-voltage NMOS or PMOS transistor, respectively, through an ion implantation process. Thereafter, a series of subsequent processes including contact and wiring processes are performed.
However, the aforementioned method of manufacturing a high-voltage device has the following problem.
That is, when forming a low-voltage well (a drift region), a maximum energy for ion implantation may be 900 KeV in a 0.35 μm semiconductor process, while a maximum energy for ion implantation may be 500 KeV in a 0.25 μm semiconductor process. For this reason, the bonding depth of a low-voltage well is shallower in the 0.25 μm semiconductor process than in the 0.35 μm semiconductor process.
Accordingly, if such a structure is implemented in the 0.25 μm semiconductor process, the electric field at an edge portion of a gate electrode of a device is not sufficiently covered so that surface breakdown may occur.